Conference Program

 

Day Time  
Tuesday, Feb. 19 9:00-12:00

WUPS tutorial

VERFE workshop

12:00-13:30 LUNCH
13:30-16:30

WUPS tutorial

VERFE workshop

 
Wednesday, Feb. 20 9:00-12:00 WUPS workshop
12:00-13:30 LUNCH
13:30-16:30

SAOS workshop

WUPS workshop

16:45-17:00 OPENING
17:00-18:00 Keynote - Jürgen Teich: Invasive Computing - The Quest for Many-Core Efficiency and Predictability
18:00-19:00 Welcome drink
 
Thursday, Feb. 21 9:00-10:00 Keynote - Lukáš Sekanina: FPGA-Based Evolvable Hardware Systems
10:00-12:00 Session

APPLICATIONS
chair: Hana Kubátová, CTU in Prague

  Tomáš Zahradnický and Róbert Lórencz Architecture of a Parallel MOSFET Parameter Extraction System
  Marcin Pietroń, Maciej Wielgosz, Dominik Żurek, Ernest Jamro and Kazimierz Wiatr Comparison of GPU and FPGA implementation of SVM algorithm for fast image segmentation
  Fabian Nowak, Ingo Besenfelder, Wolfgang Karl, Mareike Schmidtobreick and Vincent Heuveline A Data-driven Approach for Executing the CG Method on Reconfigurable High-Performance Systems
  Josef Hlaváč and Róbert Lórencz Arithmetic Unit for Computations in GF(p) with the Left-Shifting Multiplicative Inverse Algorithm
12:00- 13:00 LUNCH
13:00-15:00 Parallel Session MEMORY
chair: Wolfgang Karl, University of Karlsruhe
  Jared Sherman, Krishna Kavi, Brandon Potter and Michael Ignatowski A Multi-Core Memory Organization for 3-D DRAM as Main Memory
  Epifanio Gaona, José Luis Abellán, Manuel Acacio and Juan Fernández Deploying Hardware Locks to Improve Performance and Energy Efficiency on Hardware Transactional Memory
  Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez-Gracia, Jesús Alastruey-Benedé and Víctor Vinals-Yúfera Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors
  Tripti Warrier, Anupama B and Madhu Mutyam An Application-aware Cache Replacement Policy for Last-level Caches
13:00-15:00 Parallel Session POWER 
chair: Paul Lukowicz, DFKI & University of Kaiserslautern
  Shiao-Li Tsao, Cheng-Kun Yu and Yi-Hsin Chang Profiling Energy Consumption of I/O Functions in Embedded Applications
  Simone Corbetta and William Fornaciari Exploiting thermal coupling information in MPSoC dynamic thermal management
  Boris Motruk, Jonas Diemer, Rainer Buchty and Mladen Berekovic Power Monitoring for Mixed-Criticality on a Many-Core Platform
  Yang Xu, Bo Wang, Rafael Rosales, Ralph Hasholzner and Juergen Teich On Confident Task-Accurate Performance Estimation
15:00-15:20 COFFEE BREAK
15:20-16:50 Session RT APPLICATIONS
chair: Erik Maehle, University of Lübeck
  Tobias Ziermann, Zoran Salcic and Jürgen Teich HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN)
  Christian Herber, Andre Richter, Holm Rauchfuss and Andreas Herkersdorf Self-Virtualized CAN Controller for Multi-Core Processors in Real-Time Applications
  Josef Strnadel Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates
16:50-17:00 COFFEE BREAK
17:00-18:00 Session ALTERNATIVE TECHNIQUES
chair: Christian Müller-Schloer, Leibniz University
  Benjamin Betting, Uwe Brinkschulte, Julius von Rosen and Lars Hedrich A Highly Dependable Self-Adaptive Mixed-Signal Multi-Core System-on-Chip
  Jan Hartmann, Walter Stechele and Erik Maehle Self-Adaptation for Mobile Robot Algorithms Using Organic Computing Principles
18:45-19:45 Optional guided tour of the Prague Castle
19:45-23:00 Social Event at Vikarka (next to St.Vitus Cathedral)
Friday, Feb. 22  9:00-10:00 Keynote - Herbert Cornelius: From Milliwatts to PFLOPS – High-Performance and Energy Efficient General Purpose x86 Many-Core Architecture
10:00-11:30 Session ARCHITECTURE
chair: Christian Hochberger, TU Darmstadt
  Mageda Sharafeddine, Haitham Akkary and Doug Carmean Virtual Register Renaming
  Ahmad Lashgar, Amirali Baniasadi and Ahmad Khonsari Inter-Warp Instruction Temporal Locality in Deep-Multithreaded GPUs
  Catalin Bogdan Ciobanu and Georgi Gaydadjiev Separable 2D Convolution with Polymorphic Register Files
11:30-12:30 LUNCH
12:30-14:00 Session RECONFIGURABLE ARCHITECTURES
chair: Mladen Berekovic, TU Braunschweig
  Christian Beckhoff, Dirk Koch and Jim Torreson Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GOAHEAD
  Rico Backasch and Christian Hochberger Custom Reconfigurable Architecture based on Virtex 5 Lookup Tables
  Pascal Schleuniger, Anders Kusk, Jorgen Dall and Sven Karlsson Synthetic Aperture Radar Data Processing on an FPGA Multi-Core System
14:00-14:20 COFFEE BREAK
14:20-15:50 Session COMMUNICATION 1
chair: Jan Haase, TU Wien
  Roman Bourgade, Christine Rochange and Pascal Sainrat Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets
  Stefan Wallentowitz, Thomas Wild and Andreas Herkersdorf HW-OSQM: Reducing the Impact of Event Signaling by Hardware-based Operating System Queue Manipulation
  Arnau Prat-Pérez, David Dominguez-Sal, Josep-Lluis Larriba-Pey and Pedro Trancoso Producer-Consumer: the Programming Model for Future Many-core Processors
15:50-16:10 COFFEE BREAK
16:10-17:40 Session COMMUNICATION 2
chair: Tomáš Zahradnický, CTU in Prague
  Muhammad Nadeem, Heejong Park, Zhenmin Li, Morteza Biglari-Abhari and Zoran Salcic GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems
  Maciej Zbierski Iwazaru: the Byzantine sequencer
  Jongbeom Lim, Kwang Sik Chung, Joonmin Gil, Taeweon Suh and Heonchang Yu An Unstructured Termination Detection Algorithm Using Gossip in Cloud Computing Environments
17:40-17:50 CLOSING