Keynote 1 (Wednesday 17:00)
Invasive Computing - The Quest for Many-Core Efficiency and Predictability
University of Erlangen-Nuremberg
Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today.
In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing".
The main goal of "Invasive Computing" is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources.
The result of an invasion phase is a so-called claim of resources. After termination of computational demanding phase, the application may then release the resources again back to the pool in a phase called retreat. Now, through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties becomes possible as well.
In the talk, we provide a first language definition and for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization.
Finally, a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of the video processing algorithm to be executed as a QoS tradeoff with image quality.
Jürgen Teich (Senior Member, IEEE) received the M.S. degree (Dipl.-Ing.; with honors) from the University of Kaiserslautern, Germany, in 1989 and the Ph.D. degree (summa cum laude) from the University of Saarland, Saarbruecken, Germany, in 1993. In 1994, he joined the DSP design group of Prof. E. A. Lee in the Department of Electrical Engineering and Computer Sciences (EECS), University of California at Berkeley (PostDoc). From 1995 to 1998, he held a position at the Institute of Computer Engineering and Communications Networks Laboratory (TIK), ETH Zurich, Switzerland (Habilitation). From 1998 to 2002, he was Full Professor in the Electrical Engineering and Information Technology Department, University of Paderborn, Germany. Since 2003, he has been Full Professor in the Department of Computer Science, University of Erlangen-Nuremberg, Erlangen, Germany, holding a chair in Hardware/Software Co-Design. In 2011, he was elected member of the Academia Europaea. Since 2010, he has also been the coordinator of the Transregional Research Center 89 on Invasive Computing funded by the German Research Foundation (DFG).
Keynote 2 (Thursday 9:00)
FPGA-Based Evolvable Hardware Systems
Brno University of Technology, Faculty of Information Technology
By evolvable hardware (EHW) we usually mean either evolutionary hardware design or adaptive hardware exploiting some of the bio-inspired computing methods. The goal of adaptive hardware is to endow physical systems with a capability of adaptation in order to allow them to operate successfully in a changing environment or under presence of faults. This talk surveys principles and applications of FPGA-based evolvable hardware systems. Key parameters of EHW systems that influence the performance will be identified and various proposals to maximize the performance such as virtual reconfigurable circuits, multiple fitness units, and optimized memory access will be discussed. It will be shown that the recently introduced Xilinx’s platform, the Zynq-7000 all programmable (AP) system on-chip, has the potential to become the next revolutionary step in the domain of evolvable hardware systems.
Lukas Sekanina (IEEE Senior Member) received all his degrees from Brno University of Technology, Czech Republic (M.Eng. in 1999 and Ph.D. in 2002). He was awarded the Fulbright scholarship to work with NASA Jet Propulsion Laboratory in Pasadena in 2004. He was a visiting lecturer with Pennsylvania State University and a visiting researcher with University of Oslo in 2001. He has served as an Associate Editor of IEEE Transactions of Evolutionary Computation, and editorial board member of Genetic Programming and Evolvable Machines journal, and Int. Journal of Innovative Computing and Applications. He co-authored over 100 papers mainly on evolvable hardware. Currently, he is a Full Professor with the Faculty of Information Technology, Brno University of Technology. His research interests include evolutionary design and evolvable hardware.
Keynote 3 (Friday 9:00)
From Milliwatts to PFLOPS – High-Performance and Energy Efficient General Purpose x86 Many-Core Architecture
As we see Moore's Law alive and well, more and more parallelism is introduced into all computing platforms and on all levels of integration and programming to achieve higher performance and energy efficiency. We will discuss the new Intel® Many Integrated Core (MIC) architecture for highly-parallel workloads with general purpose, energy efficient TFLOPS performance on a single chip. This also includes the challenges and opportunities for parallel programming models, methodologies and software tools to archive highly efficient and highly productive parallel applications. At the end we will discuss the journey to ExaScale including technology trends for high-performance computing and look at some of the R&D areas for HPC at Intel.
Dr. Herbert Cornelius is Technical Director Advanced Computing at Intel EMEA. Before he was Engineering Manager in Intel’s Cluster Software & Technologies group in EMEA, focusing on scalable and parallel computing solutions based on vectorization/SIMD, multi-threading and message-passing for multi/many-core and multi-processor platforms. Prior to this position he was the EMEA Technical Marketing Manager Enterprise Computing und New Technologies enabling. He joined Intel in 1993 as Senior Computational Scientist in the Scalable Systems Division and has held various technical and management positions in the areas of Applications and Software Engineering. Before joining Intel, he served as Manager High-End Computing Europe at Fujitsu and worked at Cray Research from 1983 to 1990. Prior he worked as Scientific Assistant for Applied Mathematics at the University of Karlsruhe. He received a Ph.D. degree in Mathematics and Diploma degree in Mathematics and Informatics from Technical University of Berlin, Germany.